1. Field of the Invention
This invention relates generally to a gate array device, and in particular to a gate array device with an independent memory array region.
2. Description of the Prior Art
In FIG. 1, there is illustrated in block diagram the master chip pattern of a typical prior-art gate array with a memory array region. This type of the gate array is described, for example, in Digest of Technical Papers presented in 1983 International Solid-State Circuits Conference pp. 146-147, and in an article entitled "A CMOS Gate Array with Easily Testable Three Port RAMs" released by IEEE in 1984 (ICCD 1984).
As shown in FIG. 1, the gate array includes I/O buffer regions 1 where a plurality of I/O buffers for input and output signals are provided. The gate array also includes a basic cell region 2 and a memory array region 3. In the basic cell region 2, a number of basic cells BC are arranged in a plurality of rows 21, while in the memory array region 3, a plurality of memory arrays 35-38 and the associated peripheral circuits 31-34 are provided.
The basic cell BC of FIG. 1 comprises a pair of P-channel MOSFET and a N-channel MOSFET and is disclosed in detail, for example, in U.S. Pat. No. 4,562,453 issued to Noguchi et al. in Dec. 31, 1985.
FIG. 2 shows in functional block diagram the arrangement of the memory arrays 35-38 and the associated peripheral circuits 31-34 in the memory array region 3. Provided in the memory array region 3 are a plurality of memory cells MC arranged in arrays 35-38 for the storage of data signals. Also provided in the memory array region 3 are address buffers 31a-34a to be supplied with address signals for designating the memory cells MC; row decoders 31b-34b for decoding the address signals; and sense amplifiers 31c-34c for amplifying the data signal which has been stored in the memory cell MC designated by the address signal. Memory cells in memory cell arrays 35-38 are connected to word lines WL0-WL63 and thirty two pairs of bit lines BL and BL. The row decoders 31b-34b operate to select any one of the word lines WL0-WL63 in response to a 6-bit address signal.
Because the memory region 3 is fabricated through a master process (where transistors for the gate arrays are formed), it is a common practice to design and manufacture the memory region with a maximum possible memory capacity. By way of example the memory region may be formed as a RAM having a word length of 64 words and a bit length of 32 bits in anticipation of a user's demand. In the arrangement of FIG. 2, the memory region 3 of the storage capacity of 64 word.times.32 bit are divided into four memory arrays 35-38, each having a storage capacity 64 word.times.8 bit for the convenience of practical application.
This configuration of the memory region 3 with four arrays 35-38 of the stated storage capacities makes it possible for the user to design and arrange the memory arrays into RAMs with the storage capacity of, for example, 64 word.times.32 bit, 64 word.times.24 bit, 64 word.times.16 bit or 64.times.8 bit.
However, it is impossible to incorporate these memory arrays into a RAM having a storage capacity greater than 65 word.times.32 bit, such as a 128 word.times.16 bit or 32 word.times.65 bit configuration. This is due to the fact that the address buffer 31a, row decoder 31b and sense amplifier 31c are designed to be the peripheral circuits for the memory array 35 having a maximum fixed storage capacity of 64 word.times.32 bit. In order to avoid this inconvenience, it is necessary to provide in advance peripheral circuits compatible with a memory array of a greater storage capacity. When this is done and a memory array of a smaller storage capacity is subsequently needed and implemented, some peripheral circuits are left unused as redundancies. In addition, if it is desired to use the memory array 38 as a RAM with a storage capacity of 65 word.times.8 bit, the remaining memory cells in the arrays 38 and associated peripheral circuits for accessing them are rendered superfluous.
A prior-art construction of interest to this invention is disclosed in the aforementioned U.S. Pat. No. 4,562,453 which teaches making up all of the circuits in the memory array including the gate array of basic cells. A similar disclosure is found in a paper of IEEE entitled "A CMOS Gate Array for Computer Applications" (ICCD 1983).
Another prior art construction of interest to this invention is disclosed in a paper entitled "A CMOS GATE ARRAY with RAMs" presented in 1984 International Solid-State Device Conference (SSD 84-59).
Still another prior art construction of interest to this invention is disclosed in a paper entitled "CMOS Dual Port RAM Masterslice" which was released by IEEE in 1982 (1982 CICC). The paper describes a gate array part of which is composed of RAMs.